Automatic Preselector

1. Introduction
One of the requirements of a superhet receiver with a 455 KHz IF is a preselector at the antenna front end. Back in the day, this was usually implemented with a dual section reduced drive variable capacitor which would track an RF preselector with the variable frequency oscillator used to tune the receiver. These days with phase-lock-loops and direct digital synthesis, reduced drive variable capacitors are becoming scarce and expensive.

2. Automatic Preselector
The most straightforward solution would be to use a separate variable capacitor for the preselector and tune it by hand. This woks reasonably well, and has been used in older designs. A more modern approach would be to use a varactor diode and then come up with a way of generating the DC control voltage automatically, all of which leads us to the Passive PLL.
The Passive PLL is based on an article in Elektor Magazine (Nov. 2004) . As shown in the article’s schematic, the circuit provides a DC control voltage to the preselector’s varactor diode based on the input frequency of the VFO. The original circuit generated control voltages for frequencies from 5 to 16 MHz. I wanted to cover 3 to 8 MHz so I scaled the inductor and capacitor values as shown in the following schematic:

As shown, my version is essentially the same as the original article except for changes to C4, L1, and T1. I’ve also used a dual-gate mixer front end instead of the original common drain buffer. The VFO drive to the mixer may need to be amplified depending on the original oscillator level and the mixer type used.

2.1 Circuit Operation
To implement the Passive PLL, the VFO signal is phase shifted by C4, D1 and L1, and multiplied by the double balanced mixer U1. At the resonant frequency of C4, D1, and L1, the parallel combination of D1 and L1 appears as a resistance with a value determined by R1. C4 shifts the VFO signal by 90 degrees. The original and phase shifted VFO signals are then multiplied by U1. Checking my table of trigonometric functions, it turns out that the product of a sine wave and a cosine wave of the same frequency, is a signal of twice the original frequency. If the sine wave is shifted by other than 90 degrees, a DC offset is also generated. Capacitors C6 and C7 filter any sinusoidal outputs, and the resulting differential DC offset is applied to the loop filter consisting of U2 and associated components. The loop filter provides the DC control voltage for D1 which sets C4, L1, and D1 to resonance which in turn decreases the DC offset from U1. The same control voltage is used to set the preselector resonant frequency (suitably scaled) via D2 through R6. Trimmer VC1 is adjusted to improve the tracking linearity of the preselector resonant frequency which should be 455 KHz less then the VFO

2.2 Measurement Results
Driving the circuit from a DDS based VFO produced the following results:

fin (MHz)	Control Voltage
3.5			1.6
4.0			2.4
4.5			3.1
5.0			3.74
5.5			4.35
6.0			4.89
6.5			5.36
7.0			5.81
7.5			6.3
8.0			6.97
8.5			8.54
8.6			9.25
8.7			10.73

This produces sufficient coverage of the 3 to 8 MHz range.

3. The Simulation
I’ve always been a big fan of simulating a circuit (if possible) before I build it. If its a concept I’m not clear on (which happens a lot), I can get into the details of the circuit in ways which aren’t practical in the real world. That said, I’ve found that the results should be taken with a grain of salt. I managed to find a LTSpice model for the NE612 mixer provided by W3JDR. I managed to simulate the passive PLL portion of the circuit. The relevant files can be found here To run the simulation, unzip all the files into the same folder and load the PassivePll.asc file into LTSpice. Clicking the ‘Run’ icon in LTSpice should (hopefully) produce the transient response shown below.

As shown in the diagram, while the RF source is off, the control voltage sits at the output voltage of the NE602. This is due to the offset at U2-2. When the RF source of 4MHz is turned on at 1 msec, the mixer outputs respond to the DC offsets due to the phase change, and the differential integrator (U2) generates the control voltage. The control voltage adjusts the value of the varactor diode to the point where the mixer differential output is minimal. Any further changes in the differential output voltage will produce a corresponding correction in the control voltage.

3.1 The NE612 Model
A couple of issues with the NE612 model surfaced. Initially I had created the simulation to study the circuit. I had no luck with the transient response until I swapped the inputs to the NE602, setting Input A (pin 1) to AC ground, and setting Input B (pin 2) to the VFO input. Success, obviously an error in the schematic (its been known to happen). I went ahead and built the circuit with no luck until I swapped the inputs back to their original settings.
It turned out that there was a small error in the model. The schematic for the model is shown below:

In the original model, the external oscillator at pin 6 is connected to the base of Q2 and Q3 as shown by the red line. Comparing this to the equivalent circuit in the NE602 datasheet, the oscillator is connected to the bases of Q1 and Q4. I made the corresponding corrections in the model and voila, reality and simulation are in agreement. The problem might not have been evident in the usual NE602 application since the outputs are generally AC coupled, and there is no DC feedback involved.

The second issue surfaced while I was reviewing the Gilbert cell operation used in the NE602. All the information I could find indicated that an inverted version of the oscillator should be connected to the bases of Q2 and Q3. In this case, when Q1 and Q4 are turned on, Q2 and Q3 are turned off and vice-versa. This is what determines the double balanced mixer operation of a Gilbert cell. As shown in the model schematic (surrounded by the green rectangle) I added a capactively coupled voltage dependent voltage source (E4) to implement the inverted oscillator signal. It seems like a glaring omission in the data sheet equivalent circuit, however the only other NE602 simulation I could find¬†¬† seems to have an oscillator connected to the bases of both sets of transistors. For comparison purposes, I’ve included the original model in the simulation folder (SA612 – Orig.asc).