DDS VFO Amplifier

If you experiment with older radio receiver circuits, you notice that the selectivity for simpler designs doesn’t necessarily do well with today’s crowded band conditions. Back in the day, the solution was to use reduction drive and bandspread variable capacitors on VFOs, and while these are still available, they’re becoming increasingly expensive and rare. A good solution for the HF bands is to use a DDS based VFO controlled by a microprocessor or a PC interface. The catch is that a DDS chip on its own doesn’t necessarily have the power to properly drive an older style mixer such as (in my case) a dual-gate FET. To get around this, a wide-band amplifier is used to match the impedance and provide the necessary output levels.

1. The Circuit
The amplifier circuit I settled on is shown below. Its a variation on a common DDS amplifier circuit found on the Internet and several amateur radio books.

Q1 is a common emitter amplifier which provides voltage gain, and 180 degree phase shift from the input signal. This is followed by Q2, a common collector amplifier which provides buffering for Q1, and current gain. A portion of the output current from Q2 is fed back to the input via Rfa, Rfb and Cf to provide gain stability. The main variation I’ve added is to is to split the feedback resistance (Rfa + Rfb) and insert capacitance (Cf) between them. This has the effect of forming a bridged T network in the feedback path which develops a high impedance at the notch frequency, and compensates for the capacitance of the amplifier transistors. I’ve also used MPS5179 RF transistors instead of the usual 2N3904 because they seemed to stabilize the output level over the required frequency range in both simulations and actual measurement. Also I had a whole bunch of them.
The gain setting components in this case are feedback resistors Rfa and Rfb which can be combined into one feedback resistor Rf of 1K. The input impedance is set by Rs at 50 ohms which matches the output impedance of the DDS. The gain is set approximately by:

Av = Rf/Rs = 20

I actually measure a gain of 14 giving me an output voltage of 4V peak-to-peak.

2. Circuit Analysis
This could be the tricky part. I’ve often complained that whenever I find a circuit on the Internet or a reference book, there is often little or no explanation of how or why it works, so I’ve attempted to provide some more rigorous analysis based on my old dusty circuit theory textbooks. It would be simpler to just stop complaining.

2.1 D.C Analysis
To simplify analysis, feedback resistors Rfa and Rfb are combined into one resistor

Rf = Rfa + Rfb = 1K

The base emitter voltage of Q1 is the derived from the voltage divider on the Q2 emitter voltage:

Vbe1 = Ve2 * (Rs/(RB1 + Rf))

Due to feedback, if Ve2 increases, Vbe1 will increase, which in turn will decrease Vc1 and Ve1.
Since Vbe1 stays constant at approximately 0.7V:

Ve2 = Vbe1 (RB1 + Rf)/RB1 = 0.7 * 6 = 4.2V


IE2 = Ve2/RE2 + (Ve2 – Vbe1)/Rf = 8.9mA + 3.5mA = 12.4mA ≈ IC2
gm2 = IC2/25mV = 0.5 mho
Rπ2 = hfe2/gm2 = 100/0.5 = 200Ω


Vc1 = Ve2 + Vbe2 = 4.2 + 0.7 = 4.9V
IC1 = (Vcc – Vc2)/RC1 = (9 – 4.9)/1K = 4mA ≈ IE1
gm1 = IC1/25mV = 0.16 mho
Rπ1 = hfe1/gm1 = 100/0.16 = 625Ω

2.2. Feedback Theory Analysis
In feedback theory, this type of amplifier is described as a shunt-series configuration. This configuration is a current amplifier whose gain with feedback is defined as:

Af = Io/Ii = Ai/(1+Ai*ß)

Where Af is the closed loop current gain with feedback, Ai is the open loop current gain, and ß is the current feedback. The best way to analyze this configuration is to break the loop at the feedback resistor and analyze the circuit with the open circuit model shown below:

Where Is is the Norton equivalent circuit of the input voltage source and source resistance Rs. From the diagram, it can be seen that the current feedback expression is:

ß = -RE2/(RE2 + Rf) = -0.32

 Also, the parallel combination of RE2 and Rf is (RE2 * Rf)/(RE2 + Rf) = 320Ω.
The voltage at the base of Q1 is:

Vπ1 = I’in * [Rs // (Rf + RE2) // RB1 // Rπ1]
xxxx= I’in * [50 // 1.47K // 200 // 625]
xxxx= I’in * [48.3 // 151.5]
xxxx= 37 * I’in

– where ‘//’ denotes a parallel combination

The voltage at the base of Q2 is:

Vb2 = -gm1 * Vπ1 * {RC1 // [Rπ2 + hfe*(RE2//Rf)]}
xxxx= -0.16 * 37*I’in *{RC1 // (200 + (100 * 320))}
xxxx= -5.92 * I’in * (1K // 32K)
xxxx= -5.92 * 970 * I’in
xxxx= -5.74×103 * I’in

The open loop output current (Io’) is:

Io’ = Vb2/(Rπ2 + (Rf //RE2)
xxx= -5.7ex103 * I’in/(520)
xxx= -11 * I’in

and the open loop current gain Ai is:

Ai = I’o/I’in = -11


1+Ai*ß = 1 + (-11 * -0.32) = 4.52

so the closed loop current gain is:

Aif = -11/4.52 = -2.43

The closed loop voltage gain Av can be found as:

Av = Vo/Vi
xxx= Aif * (RE2//Rf)/Rs
xxx= -2.43 * 320/50
xxx= -15.5

A spice simulation of the circuit gave a voltage gain of about 16, while the actual circuit gave a gain of 14.

The open loop input resistance of the circuit is found by:

Ri = Rs // (RE2 + Rf) // RB // Rπ1
xxx= 36.6Ω

With feedback, the closed loop resistance becomes:

Rif = Ri / (1+Ai*ß)
xxx= 36.6 / 4.52
xxx= 8Ω

There’s a fair amount of number crunching involved but the feedback analysis does verify that the simple analysis is reasonably accurate (within a couple of dB). The main difference is due to the finite input resistance of the actual circuit versus the assumed zero input resistance of the simplified analysis. In short, the simple analysis will get you in the ballpark, but to verify the circuit, it should be either simulated or built.