HyCas AGC

1. Introduction
A few years ago I built a Shortwave Superhet receiver based on a 1991 book by R. A. Penfold. It worked surprisingly well considering its relative simplicity, and my less than optimum antenna.

One problem became apparent however, strong SSB signals seemed to noticeably produce a distorted audio signal. No amount of fiddling with the AGC circuit had any effect. With my usual twenty-twenty hindsight ( and a SPICE simulator) the answer became obvious. The front end of the receiver schematic is shown below. As shown, the first IF  transistor (Q2) is configured as a common emitter amplifier with no emitter feedback. If a stronger IF signal (ie. greater than 10 mV peak) appears at the base of Q2, the base-emitter diode is driven into its non-linear region, distorting the emitter current and hence the collector output voltage.

2. The HyCas IF Amplifier
As a solution, I finally settled on a simplified version of the HyCas IF Amplifier so called because of its use of a JFET in cascode configuration with an NPN transistor to implement a voltage controlled amplifier. The variable gain IF amplifier portion of the circuit is shown below:

followed by the AGC detector circuit:
2.1 The IF Amplifier
One of the advantages of the hybrid-cascade circuit is the high input impedance of the JFET. This simplifies the terminating impedances of the crystal filter, so two 1.5K resistors can be used for input and ouput.

As shown, the gain of each IF stage is set by a DC voltage on the base of the NPN transistor in the cascade stage. The JFET source voltage is set by the self-biasing source resistor. Changing the DC control voltage has the effect of changing the drain-source voltage JFET which in turn changes its transconductance and gain. Increasing Vagc to the point where VDS is grater than the pinch-off voltage of the JFET puts the device into saturation and no further gain changes are possible. Using the J310, the pinch off voltage Vp = 3V, and Vs = 2V therefore Vd needs to be about 5V. The drain output of the JFET is fed to the emitter input of the 2N3904, configured as a common base amplifier with the IF transformer acting as the load.

2.2 The AGC Detector
The IF output from the variable gain stage is fed to the familiar diode detector D3 with and RC filter R8 and C8. D3 is biased by diodes D1 and D2 by resistors R6 and R7 through the secondary of T3. This sets the ouput of D3 to about 0.4V and establishes the sensitivity of the detector.

The output of the detector is fed to Q5 which switches on and off depending on the sensitivity of D3. The output of Q5 is limited by to the voltage set by VR1 and R9 by diode D4. When Q5 is turned off, D4 conducts, and the voltage at the collector of Q5 limits to the voltage at VR1. When the Q5 is turned on, the collector voltage drops to Vce, close to zero. and discharges C9. This reduces the AGC voltage via buffer Q6. When the IF amplitude drops and Q5 is turned back on, C9 is recharged through D5 and R11 and Vagc is raised. Given the large time constant of C9 and R11, this has the effect providing an average Vagc to the IF amplifier.

3. Conclusions
The HyCas IF/AGC amplifier successfully solve my distortion problem. It has been used with a variety of mixer and oscillator configurations where an AM signal is taken from the D3 detector output and an SSB signal can be taken from the 455 KHz output of T3.